The invention relates to a semiconductor device, and more particularly, to a semiconductor device structure including an isolation structure and a recess gate and a method for fabricating the same.
With increased integration of semiconductor memory devices, a design rule of circuit patterns is sharply reduced. For example, as a design rule of a Dynamic Random Access Memory (DRAM) device is reduced to less than about 50 nm, formation of finer patterns is required. Such reduction in the design rule requires superior gap fill properties in a process of forming an isolation structure. In formation of the isolation structure by a Shallow Trench Isolation (STI) method, a sharp increase in an aspect ratio of the trench and a decrease in a width of the trench, makes it necessary that the insulating material for filling the trench have superior gap fill properties.
As the design rule is sharply reduced, a process of filling the trench by a High Density Plasma process has shown a limitation. Therefore, a method of filling the trench using a Spin On Dielectric (SOD), which has superior gap fill properties compared to the HDP oxide is shown in FIG. 1.
Referring to FIG. 1, a trench 13 is formed in an isolation region, which defines an active region 11 in a semiconductor substrate 10, by a selective etching process. A pad pattern having a silicon oxide (SiO2) layer 21 and a silicon nitride (Si3N4) layer 25 is formed on the active region 11. A portion of the semiconductor substrate 10 exposed by the pad pattern is then etched. A SOD 30 gap fills the trench 13. The SOD 30 is annealed for densification. Therefore, an isolation structure formed of the SOD 30 can be formed.
However, the annealing process causes a tensile stress in the SOD 30. This tensile stress is spread to the active region 11 adjoining to the SOD 30, and as a result a stress remains in the active region 11. This stress can cause slip 12 in the crystal structure of the silicon (Si) in the active region 11. This slip 12 can be generated, for example, as dislocation caused along a crystal face of the Si. The slip 12 can act as a leakage path for a carrier such as an electron or a hole during transistor operation of the DRAM device.
A refresh time of a transistor formed in the active region is lowered by the tensile stress caused in the SOD. The lowering in refresh time is particularly observed when applying a recess gate structure capable of extending a channel length of the transistor under a limited Critical Dimension (CD).
The recess gate structure generally includes a gate recess groove to extend the channel length. Spreading of the stress caused from the SOD to the bottom corner of the recess groove can result in a partial concentration of voltage to the bottom corner of the recess groove during operation of the transistor. Current leakage can be caused by this partial concentration of the voltage, and the refresh time of the memory cell of the DRAM device can be shortened accordingly.
Therefore, in order to realize an isolation structure in a device such as the DRAM device, of which design rule is sharply reduced, using the SOD, development of a method capable of lowering in operation properties of the transistor by the stress caused in the SOD is preferentially required.